The possibilities for high-performance electronics are expanded by nanowire connections.

Electronic chips are limited in area because powerful electronics require an increasing number of connections packed into a decreasing amount of space. Existing technologies are operating at the edge of physical feasibility. Researchers at Fraunhofer IZM-ASSID have now joined forces with other partners to advance a connection technique that makes use of nanometer-scale wires and is patented by NanoWired GmbH. The group gave a demonstration of how 300 mm wafers could be produced industrially using the unique process.

In order to ensure efficiency and technical autonomy in the digital age, the world requires supercomputers with great performance. Data centers must manage unfathomably large volumes of data and carry out extraordinarily intricate computations in order to provide high-performance computing. This is crucial for any complex action that must be done quickly, such algorithms or scientific simulations.

Supercomputers are already being used for high-precision medical tasks, industrial operations, logistics, and traffic flow optimization. Furthermore, there are numerous applications that call for strong, dependable, and efficient computer technology, high-performance computing being just one of them.

Innovative connecting methods are required to meet these demanding requirements. The fundamental concept is straightforward: A chip can accommodate more transistors and electrical circuits and become more powerful if its pitch, or the distance between electronic connections, is lower. Copper bumps were the traditional standard for soldering flip-chip designs, but as devices get smaller, this technology is reaching its physical limits since leaking solder can result in system short circuits.

Junior professor Dr. Iuliana Panchenko and her colleagues at Fraunhofer IZM-ASSID decided to experiment with novel interconnection approaches for contacts scaled down to less than 10 micrometers in search of creative solutions. They and their academic and industrial partners came up with a viable solution based on copper nanowires as part of the SME project “NanoInt,” and they successfully tested it for use on 300 mm silicon wafers.

A direct connection using copper nanowires has various advantages over other methods such as copper soldering, solder bumps, hybrid, and compression bonding. It is possible to build designs with varying heights thanks to the pluggable solution (nanowire to nanowire).

The resulting technology is mechanically durable, frees up a lot of design flexibility for chip designers, and requires no additional metal resources. Thin or heat-sensitive chips can benefit from this technology since connections can be established at room temperature and with little bonding pressure, saving resources.

In the first phase of the study, the researchers concentrated on finding the most uniform means to grow the nanowires at the contact sites dispersed throughout the 300 mm wafer. They achieved this by employing unique membranes that have minuscule pores. These pores can be adjusted for thicknesses ranging from 100 nm to 1 µm, and they control how thick the nanowire will become. Determining the appropriate pore diameter is essential for creating a stable and appropriately conducting connection.

After the membrane is in place, a galvanic process is initiated, allowing the copper nanowires to grow through the pores. Due to adjustments made to the procedure, the lengths of the nanowires vary by about 20%. In order to safeguard the nanowires during etching—a step required to remove the conductive copper seeding layer from the wafer—the project team also created the ideal process flow.

The researchers studied how the method may be integrated in an industrial process chain in order to assess the unique connecting technology’s practical potential. They determined the ideal assembly settings and used them in testing, paying close attention to the technology’s industrial viability, mechanical robustness, reproducibility, and homogeneity.

In order to demonstrate how the technology might be included into 2.5D to 3D system designs without the need for extra fluxing agents, the project partners constructed a 300 mm silicon wafer with homogenous nanowire bumps and nanowire connections in a chip-to-chip architecture to celebrate the project’s conclusion. Industrial applications for the technology are already underway, and more studies are aimed at getting the contacts as small as 10 or even 5 micrometers. Future developments in complicated packages utilizing fine-pitch or bigger contact surfaces may lead to new uses for nanowires.